Commits
Andy Shevchenko authored and Konstantin Khorenko committed 2ea6be4fde1
ms/x86/cpu: Keep model defines sorted by model number For better maintenance keep it sorted by numeric model ID. Add new lines to seperate model groups. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Link: http://lkml.kernel.org/r/20170316155045.50389-1-andriy.shevchenko@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> (cherry picked from commit c238f2343441e3995d2d4e993de42b072d005f4a) Signed-off-by: Jan Dakinevich <jan.dakinevich@virtuozzo.com> ================================== Patchset description: Rework the code for gathering LBR information. * Patches 1-5 pull newer definitions of Intel CPU models from upstream. * Patches 6-8 makes an attempt to rework existing implementation of LBR handling to make its further maintanance easier. * Also, patch 6 adds certain new cases from upstream to __intel_pmu_lbr_fill. However several models codes provided in intel-family.h remain unhandled. I can't find any information about these models: INTEL_FAM6_NEHALEM_G 0x1F INTEL_FAM6_CANNONLAKE_MOBILE 0x66 INTEL_FAM6_ICELAKE_X 0x6A INTEL_FAM6_ICELAKE_XEON_D 0x6C INTEL_FAM6_ICELAKE_DESKTOP 0x7D Andy Shevchenko (1): x86/cpu: Keep model defines sorted by model number Jan Dakinevich (3): Revert "ms/perf/x86/intel: make reusable LBR initialization code" ms/perf/x86/intel: make reusable LBR initialization code, part 1/2 ms/perf/x86/intel: make reusable LBR initialization code, part 2/2 Kan Liang (2): x86/cpu: Add Atom Tremont (Jacobsville) x86/CPU: Add more Icelake model numbers Peter Zijlstra (1): x86/cpu: Sanitize FAM6_ATOM naming Rajneesh Bhardwaj (1): x86/CPU: Add Icelake model number