Commits
Evgeny Kravtsunov authored and Pavel Emelianov committed 948cffc57f3
[PATCH] CPT: be carefull with MXCSR register on restore Patch introduces rst_apply_mxcsr_mask function that is to be called from rst_restore_process for masking 6 and 16-31 bits in MXCSR register if SSE2 is not supported on destination HN. When VE migrates from i386 HN with sse2 support to i386 HN without sse2 support (P3) we are facing general protection fault on restore process that uses fpu. The reason is described in Intel Architectures Software Developer's Manual (Volume 1 Basic Architecture): " 10.2.3 MXCSR Control and Status Register The 32-bit MXCSR register contains control and status information for SSE, SSE2, SSE3, and SSE3 SIMD floating-point operations. This register contains: ... * denormals-are-zeros flag that controls how SIMD floating-point instructions handle denormal source operands ... Bits 16 through 31 of MXCSR register are reserved and are cleared on a power-up or reset of the processor; attempting to write a non-zero value to these bits, using either FXRSTOR or LDMXCSR instructions, will result in a general-protection exception (# GP) being generated. ... 10.2.3.4 Denormals-Are-Zeros ... The denormals-are-zeros mode was introduced inthe Pentium 4 and Intel Xeon processor with the SSE2 extensions... In earlier IA-32 processors and in some models of Pentium 4 processor, this flag (bit 6) is reserved. Attempting to set bit 6 of the MXCSR registers on processors that do not support the DAZ flag will cause a general protection exception (# GP). " http://bugzilla.openvz.org/show_bug.cgi?id=741